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SOCC 2011: Program

9/26/2011


8:30 - 12 Noon  Plenary Session 1 - Reception Hall

Chair: Andrew Marshall, Texas Instruments Inc.


8:30 AM

Opening
Honorary Chair Prof Liang-Gee Chen


Welcome
General Chair, Program Chair

9:00 AM

Keynote: The Future Microprocessor: Return of the ASIC
Yale N. Patt, University of Texas at Austin

9:55 AM

Coffee Break

10:15 AM

Plenary: Nanosystems: Technologies and Architectures for Sensing and Computing
Prof. Giovanni De Micheli, Director, EPF, Lausanne, Switzerland

11:05 AM

Plenary: From Global Telecare Development Trends to Taiwan's Biomedical Electronic System: Opportunity and Outlook
Prof. Chih-Kung Lee, President Institute for Information Industry, Taipei

12:00: PM

Lunch - Fu Gui Room


1:20 - 4:00 PM  Digital Microfluidic Biochips - Special Session - Reception Hall

Chair: Prof. Tsung-Yi Ho, National Cheng Kung University


1:20 PM

Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore
Prof. Krishnendu Chakrabarty, Duke University

2:20PM

Recent Research and Emerging Challenges in the System-Level Design of Digital Microfluidic Biochips
Paul Pop,  Elena Maftei,  Jan Madsen
Technical University of Denmark

3:00 PM

Coffee Break

3:20PM

Recent Research and Emerging Challenges in Design and Optimization for Digital Microfluidic Biochips
Tsung-Wei Huang1,  Yan-You Lin2,  Jia-Wen Chang1,  Tsung-Yi Ho1
1National Cheng Kung University, 2Duke University


4:00 - 5:30PM  Distinguished Speakers: Embedded Tutorial - Reception Hall

Chair: Norbert Schuhmann, Fraunhofer IIS


4:00 PM

Post Silicon Debug of SOC Designs
Prof. Virendra Singh, Indian Institute of Science, Bangalore, India, Prof. Masahiro Fujita, Tokyo University, Tokyo, Japan


1:20 - 5:00 PM  Green Circuits I - Room 101

Chair: Kaijian Shi, Cadence


1:20PM

An Energy-Efficient 10T SRAM-based FIFO Memory Operating in Near-/Sub-threshold Regions
Wei-Hung Du,  Ming-Hung Chang,  Hao-Yi Yang,  Wei Hwang
National Chiao Tung University

1:45PM

A Gate Sizing Method for Glitch Power Reduction
Lei Wang1,  Markus Olbrich1,  Erich Barke1,  Thomas Buechner2,  Markus Buehler2,  Philipp Panitz2
1Institute of Microelectronic Systems, 2IBM Research & Development Boeblingen, Germany

2:10PM

Novel Adaptive keeper LBL technique for Low Power and High Performance Register files
Na Gong1,  Geng Tang1,  Jinhui Wang2,  Ramalingam Sridhar1
1University at Buffalo, SUNY, 2Beijing University of Technology

2:35PM

Integration of Code Optimization and Hardware Exploration for A VLIW Architecture by Using Fuzzy Control System
Xiaoyan Jia and Gerhard Fettweis
Dresden University of Technology, Germany

3:00 PM

Coffee Break

3:20PM

A COMPACT DELAY-RECYCLED CLOCK SKEW-COMPENSATION AND/OR DUTY-CYCLE-CORRECTION CIRCUIT
Yi-Ming Wang1,  Jen-Tsung Yu1,  Yuandi Surya1,  Chung-Hsun Huang2
1National Chi Nan University, 2National Chung-Cheng University

3:45PM

A LOW-POWER ALL-DIGITAL PHASE MODULATOR PAIR FOR LINC TRANSMITTERS
Ping-Yuan Tsai,  Tsan-Wen Chen,  Chen-Yi Lee
National Chiao-Tung University

4:10PM

A LOW POWER WIDE TUNING RANGE VCO WITH COUPLED LC TANKS
Shouxian Mou,  Kaixue Ma,  Kiat Seng Yeo,  Nagarajan Mahalingam,  Thangarasu Bharatha Kumar
Nanyang Technological University, Singapore

4:35PM

A Design Strategy for Sub-Threshold Circuits Considering Energy-Minimization and Yield-Maximization
Junya Kawashima,  Hiroyuki Ochi,  Hiroshi Tsutsui,  Takashi Sato
Kyoto University


1:20 - 3:00 PM  Analog & Biomedical Circuits I - Room 102

Chair: Dong Ha, Virginia Tech


1:20PM

A Silicon Core for an Acoustic Archival Tag
Godi Fischer and Thomas Rossby
University of Rhode Island

1:45PM

A NOVEL APPROACH TO ESTIMATE THE IMPACT OF ANALOG CIRCUIT PERFORMANCE BASED ON THE SMALL SIGNAL MODEL UNDER PROCESS VARIATIONS
Po-Yu Kuo,  Siwat Saibua,  Dian Zhou
The University of Texas at Dallas

2:10PM

Low Power 120 KSPS 12bit SAR ADC with a Novel Switch Control Method for Internal CDAC
Abhisek Dey and Tarun Kanti Bhattacharyya
IIT KGP

3:00 PM

Coffee Break


3:20 - 5:00 PM  EDA and Design Tools - Room 102

Chair: Hung-Ming Chen, National Chiao-Tung Univ


3:20PM

Simultaneous Escape Routing Based on Routability-Driven Net Ordering
JIn-Tai Yan,  Tung-Yen Sung,  Zhi-Wei Chen
Chung-Hua University

3:45PM

A CAD Methodology for Automatic Topology Selection & Sizing
Supriyo Maji and Pradip Mandal
IIT, Kharagpur

4:10PM

System Power Analysis with DVFS on ESL Virtual Platform
Wen-Tsan Hsieh1,  Yi-Siou Chen2,  Jen -Chieh Yeh1,  Shih-Che Lin1,  Hsing-Chuang Liu1
1Industrial Technology Research Institute, Taiwan, R.O.C., 2National Cheng Kung University, Taiwan, R.O.C.

4:35PM

A 65nm STANDARD CELL SET AND FLOW DEDICATED TO AUTO-MATED ASYNCHRONOUS CIRCUITS DESIGN
Matheus Moreira,  Bruno Oliveira,  Julian Pontes,  Ney Calazans
PUCRS


5:30 - 7:00 PM  Poster Session & Reception - Reception Hall

Chair: Sakir Sezer, Queens University, Belfast



DOUBLE-DIFFERENTIAL RECORDING AND AGC USING AMPLIFIER ASIC
Shin-Liang Deng,  Chun-Yi Li,  Robert Rieger
National Sun Yat-Sen University


Dynamic Calibration of feedback DAC Non-Linearity for a 4th Order CT Sigma Delta for Digital Hearing Aids Dynamic Calibration of feedback DAC Non-Linearity for a 4th Order CT Sigma Delta for Digital Hearing Aid
Syed Naqvi,  Ilker Deligoz,  Sayfe kiaei,  Bertan Bakkaloglu
Arizona State University


A REDUCED SIGNAL FEED-THROUGH 6-TAP PRE-EMPHASIS CIRCUIT FOR USE IN A 10GB/S BACKPLANE COMMUNICATIONS SYSTEM
Harry Tai,  Peter Noel,  Tadeusz Kwasniewski
Carleton University


FEASIBILITY STUDY FOR COMMUNICATION OVER POWER DISTRIBUTION NETWORKS OF MICROPROCESSORS
Rajesh Thirugnanam and Dong Ha
Virginia Tech


On-Demand Memory Sub-System for Multi-Core SoCs
Po-Tsang Huang,  Yung Chang,  Wei Hwang
Institute of Electronics, National Chiao-Yung University


WELL TAPPING METHODOLOGIES IN POWER-GATING DESIGN
Kaijian Shi1 and David Tester2
1Synopsys, 2Structured Custom


POWER-AWARE DESIGN TECHNIQUE FOR PAC DUO BASED EMBEDDED SYSTEM
Shui-An Wen,  Huang-Lun Lin,  Wei-Min Cheng,  Chi Wu,  Chun-Chin Chen,  Kun-Hsien Tsai
Industrial Technology Research Institute


Low Voltage SRAMs and the Scalability of the 9T Supply Feedback SRAM
Janna Mezhibovsky,  Adam Teman,  Alexander Fish
Ben-Gurion University


Ultra Low Power QC-LDPC Decoder with High Parallelism
Ying CUI,  Xiao PENG,  Zhixiang CHEN,  Xiongxin ZHAO,  Yichao LU,  Dajiang ZHOU,  Satoshi GOTO
IPS, Waseda University


A SAR ADC BIST for Simplified Linearity Test
Soon-Jyh Chang1,  An-Sheng Chao1,  Hsin-Wen Ting2
1National Cheng Kung University, 70101, Tainan, Taiwan., 2National Kaohsiung University of Applied Sciences


Concept and Design of Exhaustive-Parallel search algorithm to support Quality-of-service in Network-on-Chip
Meganathan Deivasigamani1,  Shaghayeghsadat Tabatabaei2,  Axel Jantsch2,  Naveed Mustafa2,  Hamza Ijaz2,  Haris Bin Aslam2,  Shaoteng Liu2
1Madras Institute of Technology, Anna University, Chennai-600044, India, 2Royal Institute of Technology, Stockholm, Sweden


TSV Sharing through Multiplexing for TSV Count Minimization in High-Level Synthesis
Wen-Pin Tu,  Yen-Hsin Lee,  Shih-Hsu Huang
Chung Yuan Christian University


Power Characteristics of Asynchronous Networks-on-Chip
Maher Rashed1,  Mohamed Abd El Ghany1,  Mohammed Ismail2
1German University in Cairo, 2The Ohio State University, Columbus, USA


DESIGN OF COMPLEX CIRCUITS USING THE VIA-CONFIGURABLE TRANSISTOR ARRAY REGULAR LAYOUT FABRIC
Marc Pons1,  Francesc Moll1,  Antonio Rubio1,  Jaume Abella2,  Xavier Vera3,  Antonio González3
1UPC, 2BSC-CNS, 3Intel


YIELD-AWARD PLACEMENT OPTIMIZATION FOR SWITCHED-CAPACITOR ANALOG INTEGRATED CIRCUITS
Chien-Chih Huang1,  Jwu-E Chen1,  Pei-Wen Luo2,  Chin-Long Wey1
1National Central University, Jhongli, Taiwan, 2Industrial Technology Research Institute, Hsinchu, Taiwan


AN ANALYTICAL MODEL TO ESTIMATE PCM FAILURE PROBABILITY DUE TO PROCESS VARIATIONS
Mu-Tien Chang and Bruce Jacob
University of Maryland, College Park

9/27/2011


8:15 - 9:10 AM  Plenary Session 2 - Reception Hall

Chair: Norbert Schuhmann, Fraunhofer IIS


8:15 AM

Boosting performance efficiency in multiprocessor systems through multi-threading
Gideon Intrater, VP - Product Marketing and Applications, MIPS Technologies


9:15 - 10:55 AM  Embedded and Multicore Systems - Room 101

Chair: Norbert Schuhmann, Fraunhofer IIS


9:15AM

Configurable Workload Generators for Multicore Architectures
Amayika Panda,  Annie Avakian,  Ranga Vemuri
University of Cincinnati

9:40AM

Computation and Communication Aware Run-Time Mapping for NoC-based MPSoC Platforms
Samarth Kaushik,  Amit Kumar Singh,  Thambipillai Srikanthan
Nanyang Technological University,Singapore

10:05AM

De-Cache: A Novel Caching scheme for Large-Scale NoC based Multiprocessor Systems-on-Chips
Azeez Sanusi and Magdy Bayoumi
The University of Louisiana, Lafayette

10:30AM

A High-Performance Low VMIN 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
Hao-I Yang1,  Shih-Chi Yang1,  Mao-Chih Hsia1,  Yung-Wei Lin1,  Yi-Wei Lin1,  Chien-Hen Chen1,  Chi-Shin Chang1,  Geng-Cing Lin1,  Yin-Nien Chen1,  Ching-Te Chuang1,  Wei Hwang1,  Shyh-Jye Jou1,  Nan-Chun Lien2,  Hung-Yu Li3,  Kuen-Di Lee3,  Wei-Chiang Shih3,  Ya-Ping Wu3,  Wen-Ta Lee3,  Chih-Chiang Hsu3
1Dept. of Electronics Eng. & Inst. of Electronics, National Chiao-Tung University, 2Faraday Technology Corporation and Dept. of Electronics Eng. & Inst. of Electronics, National Chiao-Tung University, 3Faraday Technology Corporation

10:55 AM

Coffee Break


9:15 - 10:55 AM  Verification and Test Room 102

Chair: Chien-Mo Li, National Taiwan Univ


9:15AM

Functional Verifications for SoC Software/Hardware Co-Design: From Virtual Platform to Physical Platform
Yi-Li Lin and Alvin W.Y. Su
National Cheng Kung University

9:40AM

CGA: Combining Cluster Analysis with Genetic Algorithm for Regression Suite Reduction of Microprocessors
Liucheng Guo,  Jiangfang Yi,  Liang Zhang,  Xiaoyin Wang,  Dong Tong
Dept. of Computer Science, Peking University

10:05AM

High Reliability Built-in Self-Detection and Self-Correction Design for DCT/IDCT Application
Chang-Hsin Cheng1,  Chun-Lung Hsu2,  Chung-Kai Liu1,  Shih-Yin Lin1
1Industrial Technology Research Institute, 2National Dong Hwa University

10:30AM

A Register-Transfer Level Testability Analyzer
Yen-An Chen,  Chun-Yao Wang,  Ching-Yi Huang,  Hsiu-Yi Lin
National Tsing Hua University

10:55 AM

Coffee Break


11:10 - 12:25 PM  Technology and Variation - Room 101

Chair: Ram Sridhar, University at Buffalo, SUNY


11:10AM

Monitor strategies for variability reduction considering correlation between power and timing variability.
Joan Mauricio,  Francesc Moll,  Josep Altet
Universitat Politècnica de Catalunya

11:35AM

A Parametric DFM Solution for Analog Circuits: Electrical Driven Hot Spot Detection, Analysis and Correction Flow
Rami Fathy1,  Ahmed Arafa1,  Sherif Hany1,  Abdelrahman ElMously1,  Haitham Eissa1,  Mohamed Dessouky1,  David Nairn2,  Mohab Anis3
1Mentor Graphics, 2University of Waterloo, 3American University in Cairo

12:00PM

A 144-configuration context MEMS optically reconfigurable gate array
Yuichiro Yamaji and Minoru Watanabe
Shizuoka University


11:10 - 12:25 PM  Communication Circuits - Room 102

Chair: Dong Ha, Virginia Tech


11:10AM

VLSI Design of Area-Efficient Memory Access Architectures for Quasi-Cyclic LDPC Codes
Ming-Der Shieh1,  Shih-Hao Fang1,  Shing-Chung Tang2,  Der-Wei Yang1
1National Cheng Kung University, 2Himax Technology

11:35AM

Low Power Gm-Boosted Differential Colpitts VCO
Yi-Pei Su1,  Wei-Yi Hu1,  Jia-Wei Lin1,  Yun-Chung Chen1,  Sakir Sezer2,  Sao-Jie Chen1
1National Taiwan University, Taiwan, 2Queen’s University Belfast N Ireland, UK

12:00PM

A Multi-Segment Clocking Scheme to Reduce On-Chip EMI
Behzad Mesgarzadeh,  Iman Esmail Zadeh,  Atila Alvandpour
Linkoping University - Sweden


12:30 - 1:50 PM  Luncheon Speaker - Fu Gui Room

Chair: Jiun-Lang Huang, National Taiwan University


12:30 PM

Luncheon Speaker: "SoC Test"
L.-T. Wang, President & CEO SynTest


2:00 - 4:00 PM  Software Defined Radio - Special session - Reception Hall

Chair: Prof. Hsi-Pin Ma, Tsing-Hua Univ


2:00 PM

Baseband Signal Processing in SDR
Prof. Tzi-Dar Chiueh, Graduate Institute of Electronics Engineering, National Taiwan Uinversity and Director General of National Chip Implementation Center

2:45PM

Software Defined Radio Based Frequency Domain Chaotic Cognitive Radio
Ruolin Zhou1,  Xue Li1,  Jian Zhang2,  Zhiqiang Wu1
1Wright State University, 2Texas Woman's University

3:15 PM

Coffee Break

3:30PM

CONFIGURABLE BASEBAND DESIGNS AND IMPLEMENTATIONS OF WIMAX/LTE DUAL SYSTEMS BASED ON MULTI-CORE DSP
Jen-Yuan Hsu,  Chien-Yu Kao,  Ping-Heng Kuo,  Pangan Ting
Industrial Technology Research Institute


4:00 - 5:30 PM  Distinguished Speaker: Embedded Tutorial - Reception Hall

Chair: Ramalingam Sridhar, University at Buffalo, SUNY


4:00 PM

Manufacturing Test of Systems-on-a-Chip (SoCs)
Prof. Jacob Abraham, University of Texas at Austin


2:00 - 5:10 PM  Network on Chip (Noc) - Room 101

Chair: An-Yeu Wu, Naitonal Taiwan University


2:00PM

Multi-Pheromone ACO-based Routing in Network-on-Chip System Inspired by Economic Phenomenon
Hsien-Kai Hsin,  En-Jui Chang,  Chih-Hao Chao,  Shu-Yen Lin,  An-Yeu Wu
National Taiwan University

2:25PM

FAIR RATE PACKET ARBITRATION IN NETWORK-ON-CHIP
Falko Guderian,  Erik Fischer,  Markus Winter,  Gerhard Fettweis
TU-Dresden

2:50PM

Transport Layer Assisted Routing for Non-Stationary Irregular Mesh of Thermal-Aware 3D Network-on-Chip Systems
Chih-Hao Chao,  Tzu-Chu Yin,  Shu-Yen Lin,  An-Yeu Wu
National Taiwan University

3:15 PM

Coffee Break

3:30PM

TSV-Based 3D-IC Placement for Timing Optimization
Yi-Rong Chen,  Hung-Ming Chen,  Shih-Ying Liu
National Chiao Tung University

3:55PM

Fault Tolerant Application-Specific NoC Topology Synthesis for Three-Dimensional Integrated Circuits
Yi-Xue Zheng,  Po-Ping Kan,  Liang-Bi Chen,  Kai-Yang Hsieh,  Bo-Chuan Cheng,  Katherine Shu-Min Li
National Sun Yat-Sen University

4:20PM

Exploring Virtual-Channel Architecture in FPGA based Networks-on-Chip
Ye Lu,  John McCanny,  Sakir Sezer
Queen's University Belfast

4:45PM

A Novel Methodology for Multi-Project System-on-a-Chip
Chih-Chyau Yang,  Nien-Hsiang Chang,  Shih-Lun Chen,  Wei-De Chien,  Chi-Shi Chen,  Chien-Ming Wu,  Chun-Ming Huang
National Chip Implementation Center (CIC), Hsinchu, Taiwan


2:00 - 3:15 PM  Architecture & Multimedia Systems - Room 102

Chair: Juergen Becker, Karlsruhe Institute of Technology - KIT, Germany


2:00PM

VFSMC - A CORE FOR CYCLE ACCURATE MULTITHREADED PROCESSING IN HARD REAL-TIME SYSTEMS-ON-CHIP
Siegfried Brandstätter1 and Mario Huemer2
1DICE GmbH & Co KG, 2Klagenfurt University

2:25PM

An Analog Gamma Correction Implementation for High Dynamic Range Applications
Yuan Cao and Amine Bermak
HKUST

2:50PM

Low Power tri-state Register files Design for modern out-of-order processors
Na Gong1,  Geng Tang1,  Jinhui Wang2,  Ramalingam Sridhar1
1University at Buffalo, SUNY, 2Beijing University of Technology

3:15 PM

Coffee Break


3:30 - 5:10 PM  Reconfigurable Systems - Room 102

Chair: Kaijian Shi, Cadence


3:30PM

INSTRUCTION SET CUSTOMIZATION FOR AREA-CONSTRAINED FPGA DESIGNS
Alok Prakash1,  Siew Kei Lam1,  Christopher T. Clarke2,  Thambipillai Srikanthan1
1CHiPES, Nanyang Technological University,Singapore, 2University of Bath, UK

3:55PM

HoneyComb: A Multi-grained Dynamically Reconfigurable Runtime Adaptive Hardware Architecture
Alexander Thomas,  Michael Rueckauer,  Juergen Becker
Karlsruhe Institute of Technology–Institute for Information Processing

4:20PM

COMPILER-ASSISTED TECHNIQUE FOR RAPID PERFORMANCE ESTIMATION OF FPGA-BASED PROCESSORS
Yan Lin Aung,  Siew Kei Lam,  Thambipillai Srikanthan
Nanyang Technological University

4:45PM

HIGH PERFORMANCE MULTI-ENGINE REGULAR EXPRESSION PROCESSING
Thianantha Arumugam,  Sakir Sezer,  Dwayne Burns,  Vishalini Vasu
Queen's University Belfast


6:30 - 10:00PM  Banquet Session - Kun Lun Hall

Chair: Sao-Jie Chen, National Taiwan University


9/28/2011


8:15 - 9:10 AM  Distinguished Speaker: Embedded Tutorial - Room 105

Chair: Ram Krishnamurthy, Intel Corporation


8:15 AM

Design of High-Speed Wireline Transceivers
IEEE SSCS - Distintinguished Lecturer Jri Lee


9:15 - 11:15 AM  Green Circuits II - Room 105

Chair: Ram Krishnamurthy, Intel Corporation


9:15AM

A Single-Phase Energy Metering SoC with IAS-DSP and Ultra Low Power Metering Mode
Nianxiong Tan1,  Yan Zhao1,  Kun Yang2,  Shupeng Zhong2,  Changyou Men2
1Zhejiang University, 2Vango Technologies, Inc.

9:40AM

PVT Variations Aware Optimal Sleep Vector Determination of Dual Vt Domino OR Circuits
Na Gong1,  Jinhui Wang2,  Ramalingam Sridhar1
1University at Buffalo, SUNY, 2Beijing University of Technology

10:05AM

Sleep Signal Slew Rate Modulation for Mode Transition Noise Suppression in Ground Gated Integrated Circuits
Hailong Jiao and Volkan Kursun
The Hong Kong University of Science and Technology

10:30 AM

Coffee Break


  Analog & Biomedical Circuits II - Room 102

Chair: Chung-Ping Chen, National Taiwan University


9:15AM

An Energy-Efficient OFDM-Based Baseband Transceiver Design for Ubiquitous Healthcare Monitoring Applications
Tzu-Chun Shih,  Tsan-Wen Chen,  Wei-Hao Sung,  Ping-Yuan Tasi,  Chen-Yi Lee
National Chiao Tung University

9:40AM

Design of A Neural Recording Amplifier with Tunable Pseudo Resistors
Kai-Wen Yao1,  Cihun-Siyong Alex Gong2,  Shan-Ci Yang1,  Muh-Tian Shiue1
1National Central University, Taiwan, 2Industrial Technology Research Institute, Taiwan

10:05AM

Efficient Design and Synthesis of Decimation Filters for Wideband Delta-Sigma ADCs
Rajaram Mohan Roy Koppula,  Sakkarapani Balagopal,  Vishal Saxena
Boise State University

10:30 AM

Coffee Break


10:45 - 12:45 PM  Invited Talks from IBM - Room 105

Chair: Sakir Sezer, Queens University, Belfast


10:45 AM

Technology Trends and Implications on SoC Design
Jeffrey L. Burns, IBM TJ Watson

11:30 AM

The Pending Arrival of Phase Change Memory: The Implications on the Memory-Storage Hierarchy and on Future Systems Development
Stefanie Chiras, IBM Austin Research Lab

12:15PM

FLOORPLANNING CHALLENGES IN EARLY CHIP PLANNING
Jeonghee Shin,  John Darringer,  Guojie Luo,  Merav Aharoni,  Alexey Lvov,  Gi-Joon Nam,  Michael Healy
IBM Research