For more than 23 years, IEEE SOC Conference has been providing a premier forum for the ASIC and SoC community for sharing the latest advances in technologies and applications in that area. Founded in 1987 by the IEEE chapter of Rochester, NY, USA as a local ASIC Seminar, the conference rapidly grew into a well respected international ASIC conference. As ASICs grew in complexity over the years, the IEEE ASIC Conference was one of the first conferences to pick up the trend towards System-on-Chip integration - back in 1999. Since then, the conference - first renamed IEEE ASIC/SOC and later IEEE SOCC - has emerged as the premier technical conference focusing specifically on the field of SoC development and related areas.
SOCC 2011 will be held at the Grand Hotel in Taipei, Taiwan on Sept. 26-28, 2011
In its tradition of continuing quality, SOCC 2011 will offer three days of technical papers and embedded tutorials. Please watch this site for updates on distinguished speakers and the technical program. While we are finalizing the program for 2011, you may as well want to take a look at our previous conferences.
SOCC has a long tradition of inviting high-ranking invited speakers from industry and academia to give Keynote, Plenary, and Luncheon talks. Please watch this table for updates.
Like every year, SOCC 2011 will feature a panel discussion on a hot controversial topic in the SoC area.
The authors of the best technical paper will receive a Best Paper Award
Corporate sponsors of our conference may be present with tabletop displays. For more information on corporate sponsorship, please see our sponsorship page
Like at our previous conferences, there will be several embedded tutorials during the technical program.
Yale Patt is the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin, where he directs the research of eight PhD students.
He regularly teaches the very demanding, required Introduction to Computing course to more than 400 freshmen and his advanced graduate course in Microarchitecture to those planning careers as cutting-edge computer architects.
Some of his research ideas have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his unconventional approach, "Introduction to Computing Systems: from bits and gates to C and beyond," written with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.
He has received many of the highest honors in the field for both his research and teaching, including the 1996 IEEE/ACM Eckert-Mauchly Award, and the 2000 ACM Karl V. Karlstrom Outstanding Educator Award. He is a Fellow of both the IEEE and ACM. More detail is available on his web site www.ece.utexas.edu/~patt.
SoCC started out as the IEEE ASIC Conference, moved to ASIC/SOC, and then to its current title SoCC. As the number of
transistors on a chip has increased, designers have found it useful to include, in addition to the processor, a lot of system stuff that is
in many ways orthogonal to the processor. We will soon reach the point where each chip will contain 50 billion transistors. Even after
we take into account all the system stuff, there will still be a huge number of transistors available for our use.
How do we harness them? The trend so far has been to increase the number of processor cores? I submit that there is a better way: the return of the ASIC. In this talk I will discuss why the ASIC will be particularly important for the microprocessor of 2020, and what we must do differently between now and then if we are to effectively exploit ASICs to the benefit of high performance chips.
Professor and Director, Institute of Electrical Engineering and of the Integrated Systems Centre,
EPF Lausanne, Switzerland
“Nanosystems: technologies and architectures for sensing and computing”
Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. His research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 400 technical articles.
Prof. De Micheli is the recipient of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000. He received the 1987 D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS, two Best Paper Awards at the Design Automation Conference, in 1983 and in 1993, and a Best Paper Award at the DATE Conference in 2005.
He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1987-2001). He has been Chair of several conferences, including DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989). He is a founding member of the ALaRI institute at Universita' della Svizzera Italiana (USI), in Lugano, Switzerland, where he is currently scientific counselor..
Nanosystems - based on the systematic application of nano-technologies - will create a large market of applications and a renewed
perspective for electronic design and manufacturing companies. Such systems will be the fundamental building blocks of wearable
and ambient systems, to gather and integrate heterogeneous data in real time and to operate and communicate in a wireless and ultra low power mode.
The design of these systems will be enabled by the hybridization of manufacturing technologies to attain unprecedented levels performance as well as to diversify applications by means of integrated circuits and sensors. To accomplish this ambitious goal, new technologies and architectures must be matched and tailored to the operational environment by solving novel challenging design and optimization problems, through the creation of novel design methodologies and tools.
President, Institute for Information Industry, Taipei, Taiwan, and
Lifetime Distinguished Professor, Institute of Applied Mechanics, and
Lifetime Distinguished Professor, Department of Engineering Science and Ocean Engineering,
National Taiwan University, Taipei, Taiwan
“From Global Telecare Development Trends to Taiwan's Biomedical Electronic System:
Opportunity and Outlook”
Chih-Kung Lee received his M.S. and Ph.D. degrees from Cornell University. In 1987, he joined IBM’s Almaden Research Center in San Jose, California as a Research Staff Member where his R&D work was primarily concentrated in the interdisciplinary areas related to magnetic disk drives, optoelectronic systems, metrology systems, and piezoelectric systems. He was awarded an IBM Outstanding Technical Achievement Award for his work on reducing the thermal track mis-registration of the 3.5 inch, 320 MByte, IBM 0661 hard disk file, a profitable commercial product at that time. He received two distinguished Invention Awards for his inventions and patents on laser encoders, nanometer fly height measurement systems, piezoelectric strain rate gages, and acceleration rate sensors for early shock arrival.
He joined the faculty of National Taiwan University’s Institute of Applied Mechanics in 1994. His research work on distributed piezoelectric sensors and actuators has made him a well recognized expert in the areas of flexible structure control, shock sensing, and sensor development. He has many research papers in various fields and topics and has more than 110 patents, including various technology transfers to industry. He co-founded the National Taiwan University Nano-Bio-MEMS research group, which includes not only some of the best faculty members from various institutes within the University, but also research groups from other universities. The Group’s perspective of emphasizing social responsibility as a cornerstone of a world class research team truly sets the team apart from other research teams. He is concurrently a Professor in the Department of Engineering Science & Ocean Engineering at NTU. He is an IoP Fellow and ASME Fellow.
From August 2004 to July 2007, on “loan” to Taiwan’s National Science Council, he served as Director General of Engineering & Applied Sciences. During his three years there, he led the change from a "people-centered, technology-cultural, co -development strategy" for Taiwan's engineering and applied sciences research. From October 2007 to July 2010, he held an adjunct appointment as Executive Vice-President of Industrial Technology Research Institute. He directs his efforts to finding a paradigm to link Taiwan's research in engineering and applied sciences to the next-generation industrial and societal trends. Since August 2010, he has been President of the Institute for Information Industry (III). His objectives, now and for the future, is to determine how he can help Taiwan’s industries arrive at the next stage required for transforming Taiwan from a manufacturing-based economy into an innovation-based economy.
Ageing population and decreasing birth rates are common phenomena taking place around the world. These two factors have
increased the rise of chronic diseases and have led to uneven distribution of medical resources as well as the emergence of basic
health care demands in emerging markets. Looking forth to the future, it is projected that telecare will become a major means of
coping with such issues. According to forecasts by various research institutes, the global telecare market is expected to see an annual 20% growth rate over the coming years.
In Gartner's Hype Cycle for Telemedicine, 2010 Report, mobile health monitoring and home health monitoring are listed as highly anticipated health care applications for the future and which will require advanced integration of information and communication technologies.
The medical electronics industry has been booming in recent years. With the maturation of wireless LAN (Local Area Network), Bluetooth low energy, and ZigBee technologies, it is projected that medical electronic devices will see further development in wireless connectivity, thereby providing dedicated, stable, and low-cost telecare services for the people. With its strong infrastructure and technological capability, the Taiwanese ICT industry is expected to provide ideal support for the development of telecare. Due to the vigorous involvement of the government and the industry, it is forecasted that the Taiwanese telecare industry will reach approximately US$18 billion in 2015.
This speech will analyze the global development trends of telecare and address the applications, opportunities, and future outlook for the biomedical electronics and related industries in Taiwan.
brings more than 25 years of experience in the semiconductor market. Gideon is the VP of Product Marketing and Applications at MIPS Technologies. Before joining MIPS, he was VP of
Architecture for Symwave, a global fabless semiconductor company that designs, develops and markets high-performance analog/mixed-signal integrated circuits and system solutions including USB 3.0 compliant
products that deliver 10x the speed of current USB devices.
Prior to joining Symwave, he served over 10 years as the Vice President of Solutions Architecture at MIPS where he was responsible for crafting system-level solutions for MIPS’ customers. His work led to numerous design-wins and major revenue for the company. During portions of his tenure, Giddy also ran MIPS’ product marketing functions as well, and was responsible for assimilating customer’s needs into MIPS’ product roadmap.
Prior to MIPS, Giddy spent 10 years in technical management positions with National Semiconductor Corporation, where he led the CPU and SOC architecture team and later served as a director of the Core Technologies Unit.
Giddy holds over 20 issued patents and brings a keen understanding of the embedded architecture requirements of digital consumer device designs and the challenges associated with deploying that technology.
He earned BSEE and MSEE degrees from the Technion, Israel Institute of Technology, and an MBA from San Jose State University.
Multi-threaded architectures exploit explicit parallelism to extract more throughput from a single processor. Embedded SoC designs can exploit this for greater area-efficiency, or for better real-time responsiveness. In this session, we will describe multi-threading, including how it is implemented in hardware, and how software takes advantage of multi-threading. We will offer an example of a microprocessor that implements both multiprocessing and multi-threading (MIPS32 1004K) and also share benchmarking results that demonstrate the advantages in performance, power and efficiency of a system that utilizes a combination of multiprocessing and multi-threading versus a similar system that utilizes only multiprocessing.
Laung-Terng (L.-T.) Wang, chairman and chief executive officer (CEO) of SynTest Technologies (Sunnyvale, CA), is also a visiting professor in the Department of Electrical Engineering at National Taiwan University, the Department of Creative Informatics at Kyushu Institute of Technology, and the School of Software at Tsinghua University. He received his BSEE and MSEE degrees from National Taiwan University in 1975 and 1977, respectively, and his MSEE and EE Ph.D. degrees under the Honors Cooperative Program (HCP) from Stanford University in 1982 and 1987, respectively. He worked at Intel (Santa Clara, CA) and Daisy Systems (Mountain View, CA) from 1980 to 1986 and was with the Department of Electrical Engineering of Stanford University as Research Associate and Lecturer from 1987 to 1991.
Encouraged by his advisor and professor Edward J. McCluskey, a member of the National Academy of Engineering, Dr. Wang founded SynTest Technologies in 1990. The design-for -testability (DFT) technologies Dr. Wang has developed have been successfully implemented in thousands of ASIC designs worldwide. He currently holds 25 U.S. Patents, 4 European Patents (each registered in Britain, Germany, and France), and one Chinese Patent in the areas of scan synthesis, test generation, at-speed scan testing, test compression, logic built-in self-test (BIST), and design for debug-and-diagnosis (DFD).
Dr. Wang spearheaded efforts on raising over $2 million to honor his undergraduate advisor and NTU chair professor Irving T. Ho (Stanford Ph.D., 1961), and his graduate advisor and Stanford professor Edward J. McCluskey (MIT ScD, 1956). Since 2003, he has helped establish a number of endowed chair professorships, graduate fellowships, and undergraduate scholarships at Stanford University, National Taiwan University, Tsinghua University, and Shanghai Jiao Tong University. He also co-authored and co-edited three internationally used DFT/EDA textbooks – VLSI Test Principles and Architectures (2006), System-on -Chip Test Architectures (2007), and Electronic Design Automation (2009) – with sales over 4,500 copies by December 2009.
A member of Sigma Xi, Dr. Wang received a 2007 Meritorious Service Award from the IEEE Computer Society and is a co -recipient of the 2008 IEICE Information and Systems Society Excellent Paper Award for an excellent series of papers that appeared in IEICE Transactions on Information and Systems during a period of five years. He is a Fellow of the IEEE, a Golden Core Member of the IEEE Computer Society, and serves on the 2010 IEEE Computer Society Fellow Evaluation Committee.
Continued advances in manufacturing technology have enabled an SoC design to contain billions of transistors. The increase of circuit complexity has imposed serious challenges on product quality, test cost, and system reliability. In this talk, I will give a brief introduction to SoC testing of digital circuits. Test techniques that have been practiced in industry to improve product quality and test cost are first described. A few emerging techniques to further reduce product development time and increase system reliability are then discussed.
“Post Silicon Debug of SOC Designs”
Virendra Singh, Professor, Indian Institute of Science, Bangalore, India
Masahiro Fujita, Professor, Tokyo University, Tokyo, Japan
Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on
-Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems
before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This
increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of
the internal signals. Post-silicon debug is the problem of determining what’s wrong when the fabricated chip of a new design
behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is
growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to
increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks
(processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors.
This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.
Prof. Virendra Singh obtained Ph.D in Computer Science from Nara Institute of Science and Technology (NAIST), Nara, Japan in 2005. He received his B.E and M.E in Electronics and Communication Engineering from Malaviya National Institute of Technology (MNIT), Jaipur, India. Currently, he is a faculty member at Supercomputer Education and Research Centre (SERC), Indian Institute of Science (IISc), Bangalore since May 2007. He served Central Electronics Engineering Research Institute (CEERI), Pilani, India as a Scientist for 10 years prior to joining IISc. He also served as a faculty at Department of Computer Science, Banasthali University from June 1996 to March 1997. His research interests are high performance computer architecture, testing and verification of high performance processors, VLSI testing, design for test, formal verification, fault tolerant computing, embedded system design, design for reliability, and CAD of VLSI Systems. He published about 70 research papers. He is a member of the IEEE, the ACM, the VSI, and life member of the IETE. He is a PC member of many conferences in the area of CAD and VLSI such as ICCD, DATE, ETS, ATS, VLSI Design, IOLTS, ISVLSI. He is a co-founder of RASDAT (IEEE International Workshop on Reliability Aware System Design and Test), and IWPVTD (IEEE Intl. Workshop on Processor Verification, Test and Debug) workshops.
Prof. Fujita received his Ph.D. from the University of Tokyo in 1985. He is a Professor in VLSI Design and Education Center (VDEC) at the University of Tokyo. Prior to joining the University of Tokyo in 2000, he was Director of CAD in Fujitsu Laboratories of America for 6 years. He has done innovative works in the areas of digital design verification, synthesis, and testing. He has co-authored 6 books, and has over 150 publications. He has participated and chaired many prestigious conferences in CAD and VLSI designs. His current research interests include synthesis and verification in higher level design stages, hardware/sfotware co-designs and digital/analog co-designs.
“Manufacturing Test of Systems-on-a-Chip (SoCs)”
Jacob A. Abraham
Professor of Computer Sciences, and Director, Computer Engineering Research Center,
University of Texas at Austin
Testing chips after manufacture, unlike producing transistors on a chip, does not enjoy the scaling offered by Moore's law. This tutorial will outline the increasing difficulties with manufacturing test and discuss approaches to manage the complexity of testing SoCs, including generation and design-for-test techniques for classic "stuck-at" faults as well as small delay defects which are becoming more common in scaled technologies. Issues with testing embedded analog, mixed-signal and RF modules will be addressed. Test approaches which use the computational resources within a (SoC) to test itself will also be discussed. The embedded processor in the SoC can test itself by running instruction sequences from memory. The processor can be used to test other cores in the SoC, including mixed-signal cores for analog and RF specifications, with the help of design-for-test structures such as on-chip sensors.
Jacob A. Abraham is Professor of Electrical and Computer Engineering and Professor of Computer Sciences at the University of Texas at Austin. He is also the director of the Computer Engineering Research Center and holds a Cockrell Family Regents Chair in Engineering. He received his Ph .D. in Electrical Engineering and Computer Science from Stanford University in 1974. His research interests include VLSI design and test, formal verification, and fault-tolerant computing. He has published extensively and has been included among the most cited researchers in the world. He has supervised more than 70 Ph.D. dissertations, and is particularly proud of the accomplishments of his students, many of whom occupy senior positions in academia and industry. He has been elected Fellow of the IEEE as well as Fellow of the ACM, and is the recipient of the 2005 IEEE Emanuel R. Piore Award.
“Design of High-Speed Wireline Transceivers”
IEEE SSCS - Distinguished Lecturer